Article 61651 of comp.sys.cbm:
Xref: undergrad.math.uwaterloo.ca comp.sys.cbm:61651
Newsgroups: comp.sys.cbm
Path: undergrad.math.uwaterloo.ca!csbruce
From: csbruce@ccnga.uwaterloo.ca (Craig Bruce)
Subject: 65816 progamming, Transactor
Sender: news@undergrad.math.uwaterloo.ca (news spool owner)
Message-ID: <Dzn5BA.LHG@undergrad.math.uwaterloo.ca>
Date: Mon, 21 Oct 1996 19:40:22 GMT
Nntp-Posting-Host: ccnga.uwaterloo.ca
Organization: University of Waterloo, Canada (eh!)

Yo!

I just got my copy of Issue #16 of Commodore World and inside of it is a
complete but terse listing of all of the 65816 instructions and a
description of the architecture.  This got me to playing around with the
multitasking-OS code that I wrote for C= Hacking issue #10, reworking it for
the 65816 in 16-bit mode.  I was quite impressed at how much cleaner the
code is with 16-bit operations.

Anyway, on thing that I need to know about the 65816 precisely how its
interrupts work.  When an interrupt happens while the processor is in
its Native mode, what are the exact byte-by-byte contents of information
that gets left on the stack?  With the 6502/C128ROM, the contents are:

;Stack: ($ff)      : exitaddr-1.h
;       ($fe)      : exitaddr-1.l
;       ($fd) sp+07: pc.h
;       ($fc) sp+06: pc.l
;       ($fb) sp+05: status register
;       ($fa) sp+04: .A
;       ($f9) sp+03: .X
;       ($f8) sp+02: .Y
;       ($f7) sp+01: $ff00 save
;       ($f6) sp+00: -empty-

But this obviously needs to be a little different with 16-bit registers and
the DataBank / ProgramBank registers (at least the PBR needs to be pushed
onto the stack, and the interrupt handler isn't going to get very far
without doing something with the DBR).  I need the same level of detail
as above.  Also, the article mentions that the BRK "interrupt" is handled
with its own vector, so what is the address of this vector and are there
any other differences with the interrupt vectors?

Another question is: What is CMD planning to do with addresses generated by
the CPU that are above 64K (i.e., with the 16-24 bits not all being zero)?
Are these accesses going to be subject to the current memory configuration
selected (with $01 on the C64 and $ff00 on the C128) or are they going to be
sent to the memory system unmodified to access RAM?  I hope it is the
latter, so that there is no nonsense with accessing Native memory beyond
64K.

I was a bit disappointed to see that there was no addressing mode that
accesses memory at an offset from an indirect directpage pointer, which is
very useful for accessing fields of a dynamic-data-structure record...  that
is until I figured out that that capability IS included in the familiar old
addr,X and addr,Y addressing modes.  It didn't occur to me to use this
addressing mode since I am used to the modes being effectively useless for
this purpose because of the index registers being 8 bits wide.  But, now
that they are 16 bits wide, they can be used as a base pointer for any
address in a 64K address space.  There is something to be said about having
registers being the same width as your addresses.  This makes coding a lot
easier than accessing user structures through "(zp),Y".

This brings me to another question:  What happens if you use addressing mode
directpage,X if .X contains a big number (larger than 256)?  I am guessing
that only the low byte of .X is added to the address and that the reference
wraps around on the "direct page", since this makes the most sense.

But still, I can do what I want using "absolute,X" mode, although I am going
to have to explicitly tell the assembler which mode I want to use when I
need offsets into a dynamically allocated record less than 256 bytes in.
But this gives me 16-bit offsets from a 16-bit pointer contained in either
the X or Y register for accessing memory.  from a 16-bit pointer contained
in either the X or Y register.  Instead of:

  2  ldy #10             do:        4  ldx ptr    ;(amortizable)
  2  clc                            2  clc
  5  lda (ptr),y                    5  lda @10,x
  2  adc #<1000                     3  adc #1000
  5  sta (ptr),y                    6  sta @10,x
  2  iny                           -------------
  5  lda (ptr),y                   20 == 1 us @ 20MHz
  2  adc #>1000
  5  sta (ptr),y
 ---------------
 30 == 29 us @ 1MHz

where I am using:  @ = force absolute  ...  & = force long addressing mode

  or you can even do things like:   ldx ptr
                                    inc @offset,x    ... wow!

We also get the benefit that more operations support the absolute,X mode
than do the (zp),Y mode.

Also, I recently asked Karl Hildon (The Transactor) about reprinting old
issues of The Transactor in thick volumes.  He said that each volume would
be around 500 pages, might be expensive to print in small quantities, and
that there would probably not be many people interested in this.  Well, I
ask: Are there any people out there interested in this?  Mr. Hildon said
that he might be willing go ahead with this if a few dozen other people
expressed an interest.  So, if you would be interested in such a thing, you
should send a message to Mr. Hildon expressing your interest.  His e-mail
address is "karlh@inforamp.net".

Finally, we seem to be having a bit of a problem with our local news server,
so if anyone answers any of my questions in the next couple of days, could
you also directly e-mail me a copy of your posting?  Thanks.

Keep on Hackin'!

-Craig Bruce
csbruce@ccnga.uwaterloo.ca
"'Morning After' pill for men - it changes your blood type."  --RAH


